Read-only memory (ROM) devices are commonly fabricated by employing metal-oxide-semiconductor (MOS) devices as the memory cells in a memory cell array. Each MOS device can be turned on by applying a voltage higher than its threshold voltage to a gate. To write into ROMs, ion implantation or other techniques are employed during fabrication to alter the threshold voltage of MOS devices representing particular memory cells. A desired program is thus stored in the ROM device. However, this method does not offer enough flexibility for most applications because the ROM is programmed in the middle of the overall fabrication process, and it typically takes from one-half to one month more to complete the rest of the process. Further, changes in the ROM program require a change in the ROM code mask used in the fabrication process.
Erasable programmable ROM (EPROM) devices are ROMs, but unlike ordinary ROM and PROM devices in which information cannot be changed once written, the information stored on EPROMs can be erased and rewritten. EPROMs use floating gate avalanche injection MOS (FAMOS) devices as the memory cells. In FAMOS devices, a floating gate, completely insulated by silicon dioxide, is placed underneath an ordinary gate. The floating gate can store charge which determines the threshold voltage and therefore the ON/OFF state of the device. A FAMOS device with its floating gate neutrally charged has a low threshold voltage and can be turned "ON" easily. As a result, the memory cell stores information "1". When electrons are injected into the floating gate through a thin insulation layer from the substrate, the floating gate becomes negatively charged. Since the floating gate is surrounded by the insulation layer, the electrons, once trapped, stay inside the floating gate during normal storage and operating conditions. A FAMOS device with a negatively charged floating gate has a higher threshold voltage, and so it stays "OFF"during normal operation. As a result, the memory cell stores information "0".
EPROMs are erased by flood exposure to ultraviolet light. Ultraviolet light with high enough energy excites the electrons to escape from the floating gates and also temporarily increases the conductivity of the gate oxide. Bathing the EPROM in the correct wavelength and intensity of ultraviolet light therefore lets the stored charge leak off the floating gates, causing the gates to return to an uncharged state. After about twenty minutes, information stored in all memory cells is completely purged. New information can then be written electrically into each memory cell.
Memories can be made to erase electrically by further introducing a small window with a very thin dielectric layer between the floating gate and the substrate. An implant in the substrate beneath the window area is used to provide a source for tunneling. Electrons can be injected into and withdrawn out of the floating gate through the small window by tunneling effects when voltages are applied across the thin dielectric layer. Memories with this capability are called electrically erasable programmable ROM (EEPROM) devices.
Like other ROMs, EEPROMs include, besides an array of memory cells, addressing circuitry with peripheral transistors for providing access to specific memory cells so as to enable the contents of the memory cells to be read out, or erased and rewritten. Some of these peripheral transistors, such as those controlling erasure and writing, may be required to have a high breakdown voltage, while others, used only for reading data and operating at normal signal voltages, may be allowed to have lower breakdown voltages. Grounded gate junction breakdown is due to several factors, including the gate oxide thickness, the junction impurity concentration and the junction depth. Generally, devices with a thicker gate oxide, lower impurity concentration and deeper junction have a higher breakdown voltage. In a typical process for making high breakdown voltage peripheral transistors, a phosphorus implant is performed at the drains of these transistors. The implant is then followed by a high temperature drive-in to diffuse the phosphorus under the edge of the polysilicon gate. Typical dose and depth of the implant are 5.times.10.sup.15 /cm.sup.2 and 0.5-1.5 .mu.m, respectively, and the resulting breakdown voltage is about 16-25 V. Unfortunately, the high temperature drive-in degrades the performance of other peripheral transistors. Additionally, one extra mask and one extra implant step are needed to make a high breakdown voltage device. Furthermore, for EEPROMs, a breakdown voltage of at least 20 V is desired.
It is an object of the present invention to provide a fabrication process for EEPROMs including high voltage peripheral transistors which have a breakdown voltage of at least 20 V, and which does not require an extra mask and a separate drive-in step that could degrade performance of other devices.
Another object of the present invention is to provide a fabrication process for EEPROMs with large tolerance latitudes in the process so as to produce good quality EEPROMs with high yield.